1. Field of the Invention
This invention relates to a differential sense amplifier that is typically employed as a first stage amplifier to amplify the output signals from a memory cell of a semiconductor memory array integrated circuit. More particularly, the present invention relates to an improved differential sense amplifier that is capable, among other things, of responding to input signals close to the power supply voltage after equilibration and supplying an amplified differential output signal at a new signal level.
2. Description of the Related Art
The typical differential sense amplifier is used to amplify the output signals of a memory cell of a semiconductor memory array integrated circuit (IC) that are provided over a pair of bit lines, which are typically distinguished from one another by use of the terms "TRUE" bit line and "COMPLEMENT" bit line. Each memory cell supplies two differentially related output signals that together constitute a differential signal and represent the two logical states of the cell. In one logical state, one of the cell output signals is higher than the other, and in the other logical state, the cell output signals have the opposite relative relationship. Typically, the difference between the memory cell output signals is relatively small, for example, 0.3-0.7 volts for differential sense amplifiers that use insulated gate field-effect transistors (IGFET) and 0.1 volt or less for differential sense amplifiers that are other types of transistors, such as bipolar transistors. Consequently, the typical differential sense amplifier must be capable of responding to this relatively small differential signal in order to accurately represent the logical state of the memory cell. Moreover, the smaller the differential signal to which the differential sense amplifier can respond, the faster or more responsive the differential sense amplifier is considered to be.
The array of memory cells is usually a pattern of orthogonal rows and columns. The bit lines in a typical memory array IC connect the output signal terminals of all of the memory cells in a column of the array to the output bus and the input signal terminals of the differential sense amplifier. A word line connects all of the memory cells in a row. To address a single cell in the array to read its logical state, an access signal is applied to the word line of the row containing the addressed cell, and the input signal terminals of the differential sense amplifier are connected to the bit lines of the column which contains the addressed memory cell. The output signals from the addressed memory cell create signal levels on the bit lines, and the differential sense amplifier responds to these signal levels.
One factor that adversely affects the response of a differential sense amplifier is the capacitance of the bit line and other signal conductors. More specifically, relatively long bit lines are required to connect all the cells in each column. The length of these bit lines creates a significant capacitance associated with each bit line that the cell output signals must charge or discharge before the differential sense amplifier can accurately respond to the logical state of the addressed cell. Charging or discharging the bit line capacitance delays the application of the memory cell output signals to the differential sense amplifier, which in turn delays the response of the differential sense amplifier and the delivery of an output signal from the memory array IC representative of the logical state of the addressed memory cell. Such delays adversely lengthen the access time of the memory array IC. The access time is a performance criterion of a memory array IC which relates to that amount of time between the application of an address signal and obtaining a reliable signal representative of the logical state of the addressed memory cell. Although many modern memory IC's have access times in the range of tens of nanoseconds, there is a continual need to further reduce the access time and thereby improve performance.
A well known technique for reducing the adverse effects of the bit line capacitance on the access time is to equilibrate the bit lines just before sensing the signal levels on them. Equilibration involves connecting both bit lines to a common reference potential, usually the array power supply voltage, V.sub.cc or V.sub.ss, and thereafter disconnecting the bit lines from the common reference potential so that the signals on the bit lines can move differentially toward the output signal levels of the addressed memory cell. Since the internal signal nodes of the addressed memory cell are at different levels with respect to one another, the voltage difference between the bit lines will increase as they are differentially discharged by the cell. However, due to the high loads on the bit lines when IGFET differential sense amplifiers and similar devices are employed, the output signal levels are at voltage levels that are very close to power supply voltage. Further, as previously mentioned, the voltage differences between the bit line signals is quite small at steady-state, typically on the order of 0.3-0.7 volts for IGFET based differential sense amplifiers and 0.1 volts for differential sense amplifiers that are other transistor technologies. If the differential sense amplifier has the ability to correctly respond to signal levels that are very near to the power supply voltage and to the relatively small signal difference on the bit lines even before the bit line signals reach the steady-state levels established by the cell output signals, then the response time of the differential sense amplifier will decrease, as will the access time of the memory IC. In summary, if the differential sense amplifier can respond to differential input signals very close to the magnitude of the power supply voltage, V.sub.cc or V.sub.ss, from which the bit lines start decaying after equilibration and/or to relatively small differential signal levels, then an improved response time for the differential amplifier and improved access time of the memory IC can be realized.
Additionally, typical differential sense amplifiers should achieve a high degree of amplification or gain. Generally, multiple stages of series connected differential sense amplifiers are used to obtain adequate amplification of the signals provided by a memory cell. The number of differential sense amplifier stages has a direct impact on the access time because each stage contributes an additional delay due to its own capacitance. Consequently, the higher the gain of each differential sense amplifier stage, the fewer the stages that are required and the less the access time of the memory IC.
It is also desirable that the first stage differential sense amplifier shift its output signals to levels which are better for driving the subsequent amplifier stage. Shifting the signals to a better level allows the use of differential sense amplifiers in the second and subsequent stages that are capable of fast response times and high gain. The high gain of the subsequent stages reduces the number of amplifier stages required for adequate signal amplification and, in so doing, the access time of the memory IC.
A differential sense amplifier 20 that is illustrative of the known art is illustrated in FIG. 1, and is disclosed more completely in U.S. Pat. No. 4,766,333. The differential sense amplifier is hereinafter referred to, in many cases, simply as amplifier 20. The amplifier 20 is formed using complementary metal oxide semiconductor (CMOS) field-effect transistor (FET) integrated circuit technology. The amplifier 20 includes two identical amplifier portions 20a and 20b. Each amplifier portion 20a and 20b utilizes two P-channel FETs 22a, 26a and 22b, 26b, and two N-channel FETs 24a, 28a and 24b, 28b, respectively. The transistors 22a and 24a form a reference branch of the amplifier portion 20a, and the transistors 26a and 28a form an amplifying branch of the amplifier portion 20a. The transistors 22b and 24b form a reference branch of the amplifier portion 20b, and transistors 26b and 28b form an amplifying branch of the amplifier portion 20b. One differential input signal to the amplifier 20, V.sub.in (TRUE), is applied to the amplifier portion 20a at input terminal 30a, and the other differential input signal to the amplifier 20, V.sub.in (COMPLEMENT), is applied to the amplifier portion 20b at input terminal 30b. One amplified differential output signal from the amplifier 20, V.sub. out (TRUE), is supplied by the amplifier portion 20a at output terminal 32a, and the other differential output signal from the amplifier 20, V.sub.OUT (COMPLEMENT), is supplied by the amplifier portion 20b at output terminal 32b. The two amplifier portions 20a and 20b are connected together at a single reference node 34, which commonly connects the gates of all the FETs of the amplifier 20. Further, the source terminals of transistors 24a, 24b, 28a, and 28b are connected to a reference voltage V.sub.ss at node 36.
The input signals, V.sub.in (TRUE) and V.sub.in (COMPLEMENT), provided to the amplifier 20 at the input terminals 30a and 30b are delivered by the bit lines at voltage levels that are near but slightly below the power supply voltage (V.sub.cc) for the memory array IC immediately after equilibration. The output signals at the output terminals 32a and 32b are supplied at levels generally midway between the power supply voltage (V.sub.cc) and the reference voltage at node 36 (V.sub.ss). A single reference signal exists at the reference node 34 and is applied to gates of all of the FETs of the amplifier 20. The reference signal at node 34 is established by the magnitude of the input signals at terminals 30a and 30b, and by the self-biased feedback connection of the reference branch transistors 22a, 24a, 22b and 24b, as shown.
The operation of the differential sense amplifier 20 can be understood by referring to FIG. 2A, which illustrates an inverter circuit 38. The inverter circuit 38 includes a P-channel field-effect transistor (FET) 40 that is connected to an N-channel FET 42 as shown. An input terminal 44 for providing an input signal V.sub.in to the inverter circuit 38 is connected to the gate terminals of both the P-channel FET 40 and the N-channel FET 42. An output terminal 46 for providing the output signal V.sub.out is connected to the drain terminal of the P-channel FET 40 and the drain terminal of the N-channel FET 42. Although not illustrated, the substrate of the P-channel FET 40 is connected to power supply V.sub.cc, and the substrate of the N-channel FET 42 is connected to the power supply V.sub.ss. With reference to FIG. 2B, the inverter circuit 38 provides a substantially constant high output signal for input signals with low voltages. However, once the input signal attains or exceeds a threshold voltage, the inverter circuit provides a low voltage output signal. Stated another way, the inverter circuit 38 provides a high output signal for a low input signal and a low output signal for a high input signal. The threshold voltage at which the inverter circuit 38 transitions between providing a high output signal and a low input signal is referred to hereinafter as V.sub.ref.
The inverter circuit 38 shown in FIG. 2A can also be used as a cascode amplifier 50, which is illustrated in FIG. 3A. The difference between the cascode amplifier 50 and the inverter 38 is that the voltage V.sub.ref is applied to the gates of the P-channel FET 40 and the N-channel FET 42 rather than the input signal V.sub.in . Consequently, the P-channel FET 40 and the N-channel FET 42 are now biased with V.sub.ref. A further difference is that the input signal V.sub.in is applied to the source of the P-channel FET 40 in the cascode amplifier 50 rather than a power supply signal as in the inverter 38. However, as illustrated, the substrate of the P-channel FET 40 is still connected to V.sub.cc and the substrate of the N-channel FET 42 is still connected to V.sub.ss as in the inverter 38.
For the purpose of this discussion, it will be assumed that V.sub.ref is approximately midway between the power supply voltages, V.sub.cc and V.sub.ss. In this condition, the N-channel FET 42 is in a saturated or "on" state. When V.sub.in is low, the P-channel FET 40 is in a nonconductive or "off" state because its source potential is equal to or less than V.sub.ref. As a consequence, the V.sub.out is held low by the N-channel FET 42. As V.sub.in increases, the P-channel FET 40 becomes increasingly conductive. Once the conductivity of the P-channel FET 40 exceeds the conductivity of the N-channel FET 42, V.sub.out transitions abruptly from low to high to provide an amplified version of the input signal V.sub.in. As V.sub.in continues to increase beyond this transition point, V.sub.out follows the potential of V.sub.in.
The transfer characteristic of the cascode amplifier 50 is shown in FIG. 3B by a transfer curve 52. The transfer curve 52 includes a relatively low angle first segment 54 that is representative of the operation of the cascode amplifier 50 for input signals V.sub.in prior to the transition point. The low angle of the first segment 54 indicates that the output signal V.sub.out of the cascode amplifier 50 is an attenuated version of the input signal V.sub.in. After the first segment 54 is a second or transition segment 56 that is representative of the operation of the cascode amplifier 50 for input signals V.sub.in after the transition point but prior to the point at which the output signal V.sub.out follows the input signal V.sub.in. The steep angle of the second segment 56 signifies the abrupt transition of V.sub.out from a low to a high voltage as well as an output signal V.sub.out that is a substantially amplified version of the input signal V.sub.in. Further, the second segment 56 is representative of both the P-channel FET 40 and the N-channel FET 42 operating in their respective saturation regions. Following the second segment is a third segment 58 that is representative of the operation of the cascode amplifier 50 when the output signal V.sub.out follows the input signal V.sub.in. The approximate 45.degree. angle of the third segment 58 indicates that the output signal V.sub.out produced by the cascode amplifier substantially follows the input signal V.sub.in. In other words, the third segment 58 indicates that the cascode amplifier 50 produces an output signal that is neither attenuated nor amplified from the applied input signal V.sub.in.
To utilize the circuit configuration of FIG. 2 as an amplifier, the reference voltage V.sub.ref must bias the FETs so that the average value of the input signal falls within the amplification range of the FETs. Stated another way, the reference voltage V.sub.ref must be chosen so that the average value of the input signal V.sub.in falls within the range of the second or transition segment 56 of the transfer curve 52 where both the P-channel FET 40 and the N-channel FET 42 are operating in their respective saturation regions. Biased in this manner, a slight change in the input signal V.sub.in will cause a substantial change in the output signal V.sub.out.
Moreover, to use the cascode amplifier 50 in a differential sense amplifier, the cascode amplifier 50 must be able to accommodate an input signal that can be at one of the two levels of signals that a bit line from a memory cell can provide. If the two levels of the input signal provided by a bit line fall in the attenuation or voltage following ranges of operation of the cascode amplifier 50, signified by the first segment 54 and the third segment 58, then no amplification of the input signal V.sub.in will occur. If, however, the two signal levels fall within the amplification range of operation of the cascode amplifier 50 signified by the second or transition segment 56, then the cascode amplifier 50 will produce an output signal V.sub.out that is an amplified version of the input signal V.sub.in.
Even though the difference between the two levels of signal provided by the bit line of a memory cell is relatively small, the difference may be large enough that the input signal V.sub.in to a cascode amplifier 50 will not fall within the relatively narrow amplifying range of the cascode amplifier 50. Consequently, the amplifying range of the cascode amplifier 50 must be adjusted to track or follow the input signal V.sub.in as it transitions between the two levels provided by the memory cell. Adjustment of the range of input signal V.sub.in for which the cascode amplifier 50 will provide an amplified output signal is dependent upon the value of V.sub.ref. Stated another way, changing the value of V.sub.ref changes the range of input signal V.sub.in that the cascode amplifier will amplify. The effect of changing V.sub.ref from the value of V.sub.ref associated with the transfer curve 58 is illustrated in FIG. 3C. Transfer curve 58' shows the effect of decreasing V.sub.ref from the value of V.sub.ref that exhibited transfer curve 58. Similarly, transfer curve 58" illustrates the effect of increasing the value of V.sub.ref from the value of V.sub.ref that exhibited transfer curve 58.
The amplifier 20 shown in FIG. 1 achieves a single reference signal V.sub.ref for both of the amplifier portions 20a and 20b that places them in the amplifying ranges for the input signals provided by a memory cell. Stated another way, the amplifier 20 provides a reference signal V.sub.ref that places the amplifying portions 20a and 20b in the area of operation represented by the transition segment 56 of the transfer curve 52 (FIG. 3A). The differential sense amplifier 20 shown in FIG. 1 includes, as previously mentioned, a first amplifier portion 20a for amplifying the V.sub.in (TRUE) signal provided by one of the bit lines from a memory cell and a second amplifier portion 20b for amplifying the V.sub.in (COMPLEMENT) provided by the other bit line associated with the memory cell. The first amplifier portion 20a includes an amplifying branch that is configured as the cascode amplifier 50 illustrated in FIG. 3A and is formed by P-channel FET 26a and N-channel FET 28a. Similarly, the second amplifier portion 20b includes an amplifying branch that is also configured as the cascode amplifier 50 shown in FIG. 3A and is formed by P-channel FET 26b and N-channel FET 28b. The reference signal V.sub.ref for the amplifying branch of first amplifier portion 20a is provided using the reference branch formed by the P-channel FET 22a and the N-channel 24a. So that the reference voltage, V.sub. ref, produced by the reference branch is appropriate to bias the amplifying branch of the first amplifier portion 20a in the amplification range, the P/N ratio of the reference branch FETs 22a and 24a is substantially equivalent to the P/N ratio of the amplifying branch FETs 26a and 28a. Typically, in terms of absolute size, the reference branch FETs 22a and 22b are smaller than the amplifying branch FETs 26a and 28a. Likewise, the reference signal V.sub.ref for the amplifying branch of the second amplifier portion 20b is provided using the reference branch formed by the P-channel FET 22b and the N-channel FET 24b.
Further, the P/N ratio of the reference branch FETs 22b and 24b is substantially equivalent to the P/N ratio associated with the amplifying brand FETs 26b and 28b so that the reference voltage, V.sub.ref, produced by the reference branch is appropriate to bias the amplifying branch of the second amplifier portion 20b. The absolute size of the reference branch FETs 22b and 24b is typically smaller than that of the amplifying branch FETs 26b and 28b.
The reference branches of the first and second amplifier portions 20a, 20b, are each configured as the cascode amplifier 50 shown in FIG. 3A with the addition of connections for self-biasing the transistors comprising the reference branches. More specifically, self-biasing of each of the transistors in a reference branch is achieved by connecting the gate terminal of each transistor to the drain/drain connection between the two transistors that form the reference branch. The connection of the reference branches to one another at node 34 causes the reference branches to produce a single reference signal that is approximately the average of a first reference signal approximately midway between V.sub.in (TRUE) and V.sub.ss and a second reference signal approximately midway between V.sub.in (COMPLEMENT) and V.sub.ss. This reference signal places the amplifying branches in the range of operation at which amplification occurs, represented by the second segment 56 of the transfer curve 52 shown in FIG. 3B.
Referring to FIG. 1, it can be appreciated that the two amplifier input signals 30a and 30b immediately after equilibration are at substantially the same level and thereafter drift toward the differential signal levels established by the memory cell and provided over the bit lines. Therefore each reference branch attempts to establish a slightly different self biased operating signal. But because both amplifier portions 20a and 20b are commonly connected at the reference node 34, the self biased operating signals of both portions effectively average to establish a single common reference signal V.sub.ref at the node 34.
This single reference signal at node 34 is also applied to the gates of each transistor pairs 26a, 28a, and 26b, 28b of each amplifying branch. The V.sub.ref signal, which is approximately the average of the two signals produced by the two reference branches, remains relatively constant, with an average value on the transition portion 56 of the transfer curve 52. As input signals of a small differential are applied, one input signal 30a or 30b will be slightly below the average point on the transfer curve and the other input signal 30b or 30a will be slightly above the average point. Because the transition portion 56 of the transfer curve 52 is almost vertical, the slight displacements of the input signals will result in more greatly separated output signals, thus achieving amplification.
There is also a need for a differential sense amplifier that, in addition to providing improved performance relative to the known differential sense amplifiers, conserves power by providing for its disablement when not in use.
Moreover, there is a need for a differential sense amplifier that is capable of latching the differential output signal it produces so the differential output signal is not dependent upon the continued application of an input signal to the differential sense amplifier and is capable of providing improved performance.
Additionally, a differential sense amplifier is needed that provides improved performance relative to known differential sense amplifiers as well as providing for its placement in a known state prior to use by equilibration of the input terminals and/or equalization of the output terminals.
It is against this background information relative to the prior art differential sense amplifier such as that shown in FIG. 1, and the desire to further reduce the access time of a memory array IC, as well as other considerations, that the present invention has evolved.